1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a delay locked loop (DLL), which compensates for a clock skew that causes a centering error between an external clock signal and an output data signal, and a method of compensating for the clock skew.
2. Discussion of the Related Art
Increases in the speed of a computer system's bus to 100 MHz or greater are resulting in changes to existing clock transmission techniques. In particular, clock transmission techniques have recently changed from common clock transfer techniques to source synchronous transfer techniques.
FIG. 1 illustrates a common clock transfer technique. Referring to FIG. 1, a clock signal CLK is produced separately from a data signal Din and is provided to a driver 110 via a path different than the data signal Din's path. The driver 110 transmits the data signal Din in response to the clock signal CLK, and a receiver 130 receives the data signal Din in response to the clock signal CLK.
FIG. 2 is a timing diagram of the common clock transfer technique of FIG. 1. Referring to FIG. 2, data is transmitted to the driver 110 at a first delay time (t1) after a clock edge of the clock signal CLK transitions, and the receiver 130 receives data at a sum of a second delay time (t2) and a third delay time (t3) after the time period for transmitting data to the driver 110. The first delay time (t1) denotes a period of time delayed by the driver 110, the second delay time (t2) denotes a period of time delayed while data is passing through a transmission line 120, and the third delay time (t3) denotes a period of time delayed by the receiver 130.
In the common clock transfer technique, a minimum clock period tCLKmin for synchronizing data reception with the clock signal CLK is defined in Equation 1:tCLKmin=t1+t2+t3  (1)
In the common clock transfer technique, one cannot speed up the clock CLK under the minimum clock period tCLKmin. To reduce the time t2 of the minimum clock period tCLKmin, a source synchronous transfer technique (shown in FIG. 3) has been recently introduced. Referring to FIG. 3, a transmission line 120 is installed on a data path and, a transmission line 220 is installed on a clock path. As a result, the time t2 is removed from the minimum clock period tCLKmin, thus reducing the timing uncertainty caused by the transmission line 120. As shown in FIG. 4, data received by the receiver 130 is synchronized with a clock edge of the clock signal CLK.
In FIG. 4, the clock signal CLK is supplied to internal circuits (connected to the configuration of FIG. 3) via clock buffers 210 and 230 in synchronization with the internal circuit's clocks. The delay times t1 and t3 required for the clock signal CLK to pass through the clock buffers 210 and 230 cause a clock skew, which impedes fast data transmission. To remove the clock skew, a phase locked loop (PLL) or DLL circuit is used. The PLL or DLL circuit generates a clock signal that offsets a delay time that is generated by a clock signal input buffer or a clock signal output buffer. The PLL or DLL circuit outputs data synchronous to the clock signal via the clock signal output buffer, so that the clock signal and the output data are synchronized with each other.
Synchronous memory devices, for example, synchronous dynamic random access memories (SDRAMs), are designed so that edges of the clock signal are synchronized with those of the data output from a DLL circuit. Particularly, packet-based DRAMs such as Rambus DRAMs (hereinafter, referred to as RDRAMs) are designed so that data sampling based on a clock-to-master (CTM) clock signal can occur at the middle point of a data transmission period of time (as shown in FIG. 5).
FIG. 6 is a diagram of a circuit for generating an output data signal in an RDRAM. Referring to FIG. 6, a DLL circuit 610 receives a CTM clock signal and a clock signal that is output from an output driver (OD) replication unit 620, and generates a tCLK0 clock signal and a tCLK90 clock signal that have a 90° phase difference between each other. The tCLK0 clock signal is changed into a tCLK clock signal while passing through a first path 630, and the tCLK clock signal drives output multiplexers (MUXs) 671, 672, 673, and 674. The tCLK90 clock signal passes through a second path 640, which is structured similarly to the first path 630, and is transmitted to the DLL circuit 610 via a MUX 660 and the OD replication unit 620, which compensates for time delays caused by buffers of, for example, the second path 640 and ODs, for example, ODs 681, 682 and 683. The duty of the tCLK0 clock signal is controlled by a signal that is generated by a third path 650, which has the same structure as the first path 630, and the duty of the tCLK90 clock signal is controlled by a signal that is generated by the second path 640.
Output data DQx, which is switched by the tCLK clock signal and generated by, for example, the MUX 674 and an output driver 684, is output in synchronization with a clock signal that has a 90° phase difference from the CTM clock signal. Hence, the middle points of the output data DQx are aligned with the edges of the CTM clock signal.
However, the output data DQx and the CTM clock signal may not have an exact 90° phase difference between each other, due to a difference among the time delays generated by, among others, a buffer, an interconnection line of, for example, the first, second and third paths 630, 640, and 650, the OD replication unit 620, a difference between signal paths, and a difference between the rates of dependence upon a process change. This inexact phase difference is referred to as a centering error between output data and a CTM clock signal. A Hasting DLL circuit 700, as shown in FIG. 7, is typically used to compensate for the centering error.
The Hasting DLL circuit 700 includes a phase detector (PD) 710, a final state machine (FSM) 720, an adder 730, and first and second phase mixers 740 and 750. The PD 710 detects a phase difference between the CTM clock signal and the clock signal that is output from the OD replication unit 620. The FSM 720 receives the output of the phase detector 710. The adder 730 receives the output of the FSM 720 and an offset code. The first phase mixer 740 generates the tCLK0 clock signal in response to the output of the adder 730, and the second phase mixer 750 generates the tCLK90 clock signal in response to the output of the FSM 720.
The offset code corresponds to a centering error between the CTM clock signal and the output data DQx and is offset by being added to the tCLK0 clock signal used as a timing signal for generation of the output data DQx. However, the offset code creates an additional process of searching for an optimal offset code value by communicating between a controller and an RDRAM.
Hence, there is a need for a method of determining an offset code with an RDRAM which monitors its output data and compares the phase of the output data with that of a CTM clock signal without communicating between a controller and the RDRAM.